----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:47:45 06/06/2012 
-- Design Name: 
-- Module Name:    JK_FLIP_FLOP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--		Output makes transition to 'J' value if J != K
--		output toggles if J = k = 1
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity JK_FLIP_FLOP is
	port(
		CLK		: IN STD_LOGIC;
		RST		: IN STD_LOGIC;
		
		J			: IN STD_LOGIC;
		K			: IN STD_LOGIC;
		
		Q			: OUT STD_LOGIC
		
	);
end JK_FLIP_FLOP;

architecture Behavioral of JK_FLIP_FLOP is
	signal Q_internal			: std_logic:=0;
begin
	JKFF : process(RST, CLK)
	begin
	  if RST = '1' then
		 Q <= '0';
	  elsif rising_edge(CLK) then
		 if J /= K then
			Q_internal <= J;
		 elsif J = '1' and K = '1' then
			Q_internal <= NOT Q_internal;
--		 elsif J = '0' and K = '0' then
			
		 end if; 
	  end if;
	end process JKFF;

	Q <= Q_internal;

end Behavioral;

